early access β€” the waitlist is open

circuit simulation from prompt to waveform

describe the circuit in plain language. the agent writes the netlist, picks the analysis, runs the solver, and answers your questions about the result. built for people who want answers, not seat licenses.

session.logreplay

loading cartridge

scope β€” ch1 run
v(out) Β· rippleΞ”v β‰ˆ 34 mV

this transcript is an illustration β€” but the loop is live: boot the agent and it runs a real solver on your prompt, right now.

speaks the formats engineers already trust

ngspiceVerilatorIcarus VerilogYosysGTKWaveKiCadWaveDromSPICE .cirngspiceVerilatorIcarus VerilogYosysGTKWaveKiCadWaveDromSPICE .cir
// how it works

from setup-heavy eda to intent-driven simulation

the old way is a week of meshing menus and solver dialogs. the new way is a conversation that happens to end in a converged simulation.

describe01

say what the circuit is and what you want to know. plain language, no netlist syntax.

review02

the agent shows you the netlist, sources, and analysis plan it wrote. you approve or correct.

run03

the solver executes on pooled compute. transient, ac, dc sweep β€” whatever the question needs.

probe04

waveforms, operating points, and margins come back as plots you can read, not raw logs.

ask05

β€œwhy does it overshoot?” β€œwhat if the load doubles?” β€” the agent answers from the results.

iterate06

every follow-up refines the same design. the loop stays short, like a repl for hardware.

β†Ί step 06 loops back to 01 β€” that is the point.

// use cases

the circuits people actually lose weeks on

⚑

power electronics

buck and boost converters, ripple and efficiency, gate-drive sanity checks before you burn a board.

"simulate a 5v→3.3v buck at 500 khz, show output ripple."

γ€°

analog front-ends

filters, op-amp stages, sensor chains β€” frequency response and noise without opening a single dialog box.

"design a 2nd-order low-pass at 1 khz and sweep it 10 hz–100 khz."

πŸ•Ή

digital logic

rtl sanity, counters and fsms, timing questions β€” verilog in, waveforms and answers out.

"run this counter at 50 mhz and show me where it glitches."

a seat license costs more than the engineer's laptop.

professional simulation tooling is gated behind five-figure licenses and hundred-page manuals. the solvers underneath are open β€” what is missing is the layer that speaks human. that layer is what we are building.

// pricing

free where it teaches, paid where it earns

hobbyists & students

free

small circuits, full workflow. learn faster, stop getting blocked by setup complexity. free forever for little netlists.

engineers

free in beta

bigger circuits, longer transients, exports. free while we are in early access β€” no credit card, feedback is the price.

companies & teams

talk to us

standardize the workflow, give everyone on the team access to simulation, keep the results in your pipeline.

// press start

start with a prompt. end with a waveform.

the agent is in the lab. the waitlist is live β€” leave a contact and you get a key at boot, in the order you arrived.

early-access.reginsert coin
no spam. one email when the agent boots.